Neural signal acquisition systems require very low-power interfacing circuitry for implantable operations. It has been shown that reconfigurable SAR ADCs provide the most suitable characteristics for this low-power and low-speed applications. For a high-fidelity acquisition, the signal should be sampled at 20kHz with 10 bit resolution. This project presents an ADC for neural signal applications with merged-capacitor switching (MCS) and ternary SAR (TSAR) algorithm. Further, we added asynchronous logic for achieving a very high energy efficiency.

Top Level Architecture of TSAR

The design expands on the novel ternary SAR architecture by optimizing it for neural signal acquisition. It includes novel features a more power efficient quantizer with an accurate time reference usage and asynchronous logic design. The capacitor array was optimized for mismatch in the IBM 0.13um technology. The designed ADC samples at 500 kS/s with 10-bit resolution, while consuming 2.0 uW of power. The ADC achieves the ENOB of 8.46, maximum DNL of 1.5 and INL of -3.3, and final FOM of 11.36 fJ/conv-step.

The Concept of Ternary Logic

Whereas in a regular binary SAR, every comparison gives a binary decision about the input with respect to a reference, in TSAR, we can make 3 decisions about the input as shown in figure. In J. Guerber’s paper, it is proven that the comparator metastability time provides reliable information about the absolute value of the input voltage. Thus, by timing the comparator output, we can arrive at 3 conclusions: the comparator can make either binary decision in the allotted time; if it does not, we can determine the input is closer to the reference level and give it a 3rd option, or the “0.5 bit”. This extra information can be used in a number of ways and in our architecture, we use it to reduce DAC switching, to skip stages, and to gain an extra bit of resolution.

**Simulations on the Number of Comparisons and Switching**

We explored the effectiveness of TSAR based on MATLAB simulation. The number of comparisons and switched capacitor changes depending with the input voltage. However, on average, the MCS-TSAR ADC reduces the number of comparisons by 2.422 and number of switched caps by 310.47 from a conventional binary SAR. Also, due to the extra bits gained through MCS algorithm and residue shaping, we can reduce the DAC resolution by 2 bits.

**Merged Capacitance Switching with Bottom-Plate Sampling**

The quantizer consists of a dynamic voltage comparator and latches connected to the comparator output. By latching the comparator outputs at defined times, we can apply the timing reference and gain the extra 0.5 bits. Speaking of DAC, The capacitive DAC only needs 8 switchable capacitors due to use of MCS and residue shaping algorithms. Each bit is connected to four voltages: Vin, 0, Vref/2, and Vref, describe in the figure. We perform bottom-plate sampling for constant charge injection. Because of the low sampling speed, we are able to use transmission gate sampling without significant input signal degradation.

**Logic Schematic and Timing Diagram**

The logic implementation is performed in such a way of minimizing switching activity. The asynchronous feature allows us to reduce switching power consumption from clocking and also leads to better performance. In order to perform successive stage operations without clock, our TSAR logic utilizes edge signals from the comparator and the time quantizer. Once logic triggers the comparator after the initial sampling stage following input global clock, comparator and logic delay lines trigger each other in order to compute the output bits. Diagram shows the block diagram of asynchronous TSAR logic, it is largely divided into counters and skipping logics. One-hot-ring counter takes the advantage of minimized switching by only changing adjacent two bits. Since the counter have to be reset at the beginning of every cycle, one-hot-ring counter is more efficient than typical ring counter. Current state is determined by where which flip-flop retains ‘1’. When comparison is made, a pair of flip-flops in an active state fetch comparator outputs. Other flip-flops stay opaque and do not switch. As a result, each flip-flop takes comparator result once in a clock cycle and the number of switching is minimized. More importantly, logic operation can be skipped within a reference group. When the comparator is in the metastable range, a skipping logic takes ‘00’ or ‘11’ code. Then, it sends skipping signal directly to following stages in a reference group notifying them to ignore inputs.

**Comparison with State-of-the-art ADCs**

In conclusion, our 10-bit ternary SAR ADC achieved good performance for schematic simulations, with an ENOB of 9.5 bits. However, after PEX extraction of our comparator, the ENOB dropped significantly by 8.69. Although ENOB is not so competitive, it has comparable FOM because of low power consumption. We would need to improve the performance of our comparator, since it consumes little power compared to the DAC. The MCS switching structure and ternary algorithm is an effective way to reduce DAC power, but it is still dominant in our design.

**Team Members : JiHong Phelix Min, Adam Mendrela, Allan Wang**